1. Field of the Invention
This invention relates to a receiving portion of a radio communication device such as a mobile telephone set.
2. Description of the Related Art
Some mobile telephone sets have receiving portions which periodically fall into a sleep mode of operation. When the receiving portion is in the sleep mode of operation, most of circuits in the receiving portion are deactivated to save electric power. At an expected timing of the transmission of polling signals from a base station, the receiving portion changes from the sleep mode of operation to an awake mode (a normal mode or a stand-by mode) of operation.
UK patent application GB 2297884 A corresponding to Japanese published unexamined patent application 8-251656 discloses a power saving arrangement in a mobile telephone. In UK patent application GB 2297884 A, the mobile telephone has a high frequency system clock, and a processor arranged to process polling signals received while the telephone is in its stand-by condition.
When polling signals are not being received, it is possible for the telephone to be placed in a sleep condition by deactivating the system clock. Re-activation occurs in response to a calibrated number of clock cycles produced by a lower frequency sleep clock. Upon re-activation, system clock counters specifying sub-frame periods and frame periods are re-loaded so that they can be re-activated at the required phase. The phase of these counters is compared with signals received from base stations and modifications are made to system counts as required. The extent to which modifications are required is also used to re-calibrate the sleep clock.
In the power saving arrangement of UK patent application GB 2297884 A, the timing of re-activation is determined by the sleep clock. The re-activation includes re-activation of received-signal processing. Accordingly, a minimum increment or a minimum decrement (a minimum variation unit) of the timing of re-activation of the received-signal processing corresponds to the period of the sleep clock. Thus, it is difficult to vary the timing of re-activation of the received-signal processing by a unit shorter than the period of the sleep clock.
In the power saving arrangement of UK patent application GB 2297884 A, the sleep clock is re-calibrated in response to the result of the comparison between the phase of the system clock counters and the phase of the signals received from the base stations while a frequency error of the sleep clock is not detected.